This invention relates generally to large scale integrated circuits and more particularly to read only memories wherein binary information is permanently stored.
A basic device for the operation of general purpose computers and the operation of processor controlled equipment where the use of permanent data is required is the read only memory (ROM). Low cost, compact read only memories have made possible the use of many devices which can utilize extensive permanent data for more effective operation, but cannot support a large overhead cost. The advent of large scale integration using field effect transistor (FET) circuitry has made permanent storage using such devices competitive with any other form of random access storage.
To achieve high density ROM design it is necessary that both the power consumption that results in heat that must be dissipated be minimized and the overhead circuits associated with the array which require space or real estate on the chip and limit compactness be eliminated. The use of dynamic circuits yield compact size hence the relative size of diffusions is not a factor and the circuitry can be designed for easy access and the elimination of DC circuits that result in heat dissipation problems. The limitation in regard to dynamic circuitry is the necessity of clocked timing circuits and interfacing with exterior static logic with which the device must be connected and interact.
The ROM of the present invention utilizes dynamic techniques for both an FET array arranged in rows and columns and the column address where a control electrode interconnects the gate elements of a column of bit positions. The array is composed of bit locations each of which is an FET device capable of indicating either a logical one or a logical zero at an output upon being addressed. A logical one occurs when effective transistor action occurs because of the presence of a thin oxide gate and a logical zero occurs when no transistor action results upon the bit location being addressed as a consequence of the absence of a thin oxide gate. Accordingly, each bit location is personalized by the presence or absence of such a gate or device. Each bit location also has two output electrodes. A source line addresses a row of devices by placing a charge at the source of each FET in a selected row. A bit position is selected by the intersection of a column or gate line and a row address or source line. If a gate is present at the bit location the charge from the source line is transferred to the sense or drain line to indicate a logical one at an associated output terminal. If a device or thin oxide gate is absent, then a logical zero is indicated. The array uses compact non-ratioed dynamic circuity which indicates logic levels through a charge transfer without the use of DC current. The gate decode or column address circuitry is also non-ratioed dynamic circuitry having minimal space requirements. The remainder of the circuitry is composed of ratioed static circuits including the gate decode address, source address and decode circuits, chip or array address and decode circuits, the sense circuits and output latches. Each of the circuits that connect with other devices are static and therefore may interface with any static chip.
To coordinate the dynamic logic, two clock pulses are utilized. A first clock pulse .phi.X is utilized to time the charging of the selected gate decode line and a second clock pulse .phi.P serves both to ground any residual charge on an output or sense line from the previous cycle and to time the source line select for the current cycle. When an address is received by the gate decode, the previously charged gate line is grounded if the same line is not readdressed. However, it is possible for a charge to remain on the sense line from a previous cycle if provision is not made for removal of the charge from the sense line at the conclusion of the cycle or after the output has been latched. To remove any resident charge on the output line an additional column of bit positions is provided in the array each of which has a device or gate which is addressed by the clock pulse +.phi.P to provide a conductive path from each sense line to the associated source line while an additional FET in each source line decode circuit is also activated by clock pulse +.phi.P to complete the path to ground.
The output of the ROM cycle is latched when .phi.P again returns to a + value and will remain valid while .phi.P continues to have a positive value. The output latches are reset by removing the positive input charge from the reset inverter while .phi.P continues to have a positive value. By using the techniques described above it is possible to achieve a density of 24,576 bits of read only storage along with the associated address, array select and output sensing and latching circuitry in a space less than 200 mils square.
It is an object of this invention to provide an improved high density read only memory. It is a further object of the invention to provide an increased density read only memory by optimizing placement of array elements and reducing power consumption. It is also an object of the invention to provide a read only memory that utilizes dynamic logic in the array while using static logic for addressing and sensing to enable ease of interface with static logic chips. It is also an object of the invention to provide a read only memory with means to remove any charge resident in the sense line at the end of a memory cycle.